New silicon chips undergo many tests throughout the development and testing cycle. For example, design testing is done early in the development cycle of a product and debugging is done during production of the product. One test performed on silicon chips involves the internal circuitry delay (i.e. the propagation delay) through structures on the chip. Internal circuitry delay is tested by providing a pulse of a known length to an oscillating device, such as an inverter ring, implemented on the chip, and then counting the number of state value toggles by the oscillating device that occur during the length of the pulse. The number of state value toggles during the pulse is inversely proportional to the internal circuitry delay. It is preferable to implement all of these functions on a single chip.
Conventionally, a multi-function tester is used to perform many of the tests required for a chip, including testing the internal circuitry delay. FIG. 1 is a block diagram of a multi-function tester 110 and a chip 120 undergoing testing. Multi-function tester 110 provides a pulse P of known duration to chip 120. A counter (not shown) implemented on chip 120 counts toggles of an inverter ring (not shown) implemented on chip 120 and provides this number back to multi-function tester 110 as a count C. Multi-function testers such as that multi-function tester 110 are quite expensive and are typically in heavy use. As a result, obtaining time to test a chip for internal circuitry delay requires scheduling time for use of the multi-function tester, as well as the initial cost of obtaining the multi-function tester.
The internal circuitry delay may also be tested directly without resorting to a multi-function tester. FIG. 2 is a block diagram of a conventional pulse generation circuit 200 used for such a direct test. Pulse generation circuit 200 includes a 5-bit binary counter 210, an NAND gate 220, and a pulse generator 230. A transition to a logic “1” value of a trigger signal TRIGGER sets an initial value of binary counter 210 (e.g. 5) and causes binary counter 210 to count clock pulses of clock signal FFCLK, decrementing the count down to a particular value (e.g. 0). Count data lines 212 carry the binary count of the binary counter 210. For example, when a 5-bit binary counter is set to a value of 5, count data lines carry a binary “00101” value.
NAND gate 220 has a plurality of input terminal invertedly coupled to count data lines 212. As a result, a decrement of the count of binary counter 210 to 0 will cause all input terminals of NAND gate 220 to receive logic “1” values, thereby causing a logic “0” value of count indicator signal C to appear at the output terminal of NAND gate 220. By uninverting one or more of the input terminals for a particular application, counter 210 may count down to a number other than 0. In this way, NAND gate 220 is programmed to indicate when a particular count of binary counter 210 has been reached by causing count indicator signal C to transition to a logic “0” value. A similar conventional method uses an OR gate in place of HAND gate 220.
Pulse generator 230 provides a pulse signal P beginning from the time a logic “1” value of trigger signal TRIGGER is received. Pulse generator 230 maintains logic “1” pulse signal P as long as a logic “1” count indicator signal is received from NAND gate 220. Pulse signal P transitions to a logic “0” upon completion of the count of binary counter 210. The result is a pulse signal P that has a width indicated by the particular count of binary counter 210. Glitches occur in the value of count indicator C due to timing differences in the receipt of values on count data lines. For example, in transitioning from a count value of 2 (e.g. “00010”) to a count value of 1 (e.g. “00001”), the least significant bit may transition to a logic “1” value after the next significant bit transitions to a logic “0” value. In this situation, a binary “00000” is briefly applied to NAND gate 220, causing a glitch in count indicator C. Glitches such as these can cause confusion as to when to end the pulse generated by pulse generator 230.
It would be desirable to generate a glitchless pulse of known duration using minimal logic without resorting to the use of expensive testing equipment.